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CLOCK DATA データシート, Datasheet

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詳細検索 : 'Clock Data ' - 結果は: 20709 (1/1036) Pages
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Winbond
W9725G6KB-25 DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask
W9412G6JH-5 Double Data Rate architecture; two data transfers per clock cycle

Micrel Semiconductor
SY87721L 3.3V 28Mbps-2.7Gbps ANYRATE CLOCK AND DATA RECOVERY WITH INTEGRATED CLOCK MULTIPLIER UNIT

Winbond
W9725G6JB25I Double Data Rate architecture: two data transfers per clock cycle

Micrel Semiconductor
SY87721L_08 CLOCK AND DATA RECOVERY WITH INTEGRATED CLOCK MULTIPLIER UNIT

Texas Instruments
DS99R421_14 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DC DCBalanced)

Renesas Technology Corp
SH7136_09 SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer

Winbond
W631GG6KB-15 Double Data Rate architecture: two data transfers per clock cycle

Texas Instruments
DS99R421_15 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DC Balanced) Converter

Winbond
W972GG6JB-25 Double Data Rate architecture: two data transfers per clock cycle

National Semiconductor ...
DS99R421 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to Single Embedded Clock DC-Balanced LVDS Converter

Winbond
W9412G2IB4 Double Data Rate architecture; two data transfers per clock cycle

National Semiconductor ...
DS99R421_08 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to Single Embedded Clock DC-Balanced LVDS Converter

Winbond
W9751G6KB-25 Double Data Rate architecture: two data transfers per clock cycle

ON Semiconductor
NB6L16_07 2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/Translator Buffer

Micrel Semiconductor
SY87701V_08 5V/3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY

Agere Systems
LG1600KXH LG1600KXH Clock and Data Regenerator
1345 1345-Type Receiver with Clock Recovery and Data Retiming

Integrated Device Techn...
5T905 2.5V Single Data Rate1:5 Clock Buffer Terabuffer

Analog Devices
AD800_15 Clock Recovery and Data Retiming Phase-Locked Loop

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